| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_33cf281df1fdf76b7da1bb88a75ba80d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2320-0257
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2320-0252
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0243
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0218
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0291
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2320-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2330-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2310-0264
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G2230-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3233
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3275
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09G3-3258
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C19-28 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-3266
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-3225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-32 |
| filingDate |
2020-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7077aa69826c9edef96eaae5f6e9b297 |
| publicationDate |
2021-07-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-113066446-A |
| titleOfInvention |
Gate driving circuit and light emitting display device including the same |
| abstract |
Disclosed are a gate driving circuit and a light emitting display device including the same, in which current leakage of a control node can be prevented. The gate driving circuit includes first to mth stages of circuits, wherein each of the first to mth stages of circuits includes: first to fifth control nodes; a node control circuit that controls a voltage of each of the first to fourth control nodes based on the first forward bit signal; a sensing control circuit which controls a voltage of the fifth control node based on the line sensing preparation signal, the second advance bit signal, and the first reset signal; and a first node reset circuit controlling a voltage of the first control node based on a voltage of the fifth control node and the second reset signal, wherein the first node reset circuit may include a discharge path having two thin film transistors connected between the gate low potential voltage line and the fifth control node. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023097477-A1 |
| priorityDate |
2019-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |