| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0928
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823871
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-743
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5286
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 |
| filingDate |
2020-11-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d40711f2e9e0cb6974045971628b43f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e1581566ce78b9443f62fa52a768587a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_37bcc4016096bee9c0848dd8f49fad00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0b6233a4c496bfd6a9ae1287130e4e6a
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ec4f53dc8113f494452dcdf298e812ec |
| publicationDate |
2021-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-113053887-A |
| titleOfInvention |
Semiconductor structures and methods of forming integrated circuit structures |
| abstract |
The present disclosure provides embodiments of a semiconductor structure. The semiconductor structure includes: a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; and a first source/drain feature formed on on the active area and disposed at the edge of the gate stack; a backside power rail formed on the backside of the substrate; a backside contact feature interposed between the backside power rail and the first source/drain feature and electrically connect the backside power rail to the first source/drain feature. The backside contact feature also includes a first suicide layer disposed on the backside of the substrate. Embodiments of the invention also relate to methods of forming integrated circuit structures. |
| priorityDate |
2019-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |