| abstract |
A method for fabricating an integrated circuit includes receiving an IC design layout defining a semiconductor structure, the semiconductor structure having via rails extending longitudinally in a first direction, and the via rails contacting in a second direction perpendicular to the first direction Vertically extending source contact. The method also includes using pattern recognition on the IC design layout to identify via rails, source contacts, drain contacts at a distance from the source contacts, and gate structures sandwiched between the source and drain contacts . The method also includes determining locations, lengths, and widths of protruding vias to be incorporated into the IC design layout. The method also includes adding protruding vias having the determined length and width to the IC design layout at the determined locations to provide a modified IC design layout. |