http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112564708-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ce5a555d83dcd6662ca4874440e651a0 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-186 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-18 |
| filingDate | 2020-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1589af3d67fb30bf2304907d31f3ff5f |
| publicationDate | 2021-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-112564708-A |
| titleOfInvention | Analog-to-digital conversion circuit |
| abstract | The invention discloses an analog-to-digital conversion circuit which comprises a feedforward Sigma-Delta analog-to-digital conversion module, a buffer module, a first chopping unit and a second chopping unit, wherein the feedforward Sigma-Delta analog-to-digital conversion module is connected with the buffer module; the first chopping unit is used for chopping a first offset voltage generated by the buffer module and a second offset voltage generated by the sampling capacitor assembly and outputting the chopped first offset voltage and the second offset voltage to the secondary integrator; and the second chopping unit is used for chopping the third offset voltage generated by the integrating capacitor assembly and outputting the third offset voltage to the sub-integrator. The invention carries out chopping processing on offset voltage caused by each part of a circuit including a high-order feedforward Sigma-Delta analog-to-digital conversion module by arranging a chopping unit and corresponding control logic in the analog-to-digital conversion circuit, and outputs the offset voltage in the analog-to-digital conversion circuit to a relatively high-frequency position of the circuit so as to eliminate the offset voltage through subsequent processing, thereby optimizing the performance of the analog-to-digital conversion circuit. |
| priorityDate | 2020-12-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.