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filingDate 2020-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4405fcee731ae1864bc88ac73d2b5a3e
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publicationDate 2021-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-112382629-A
titleOfInvention A packaging structure of stacked wafers and packaging method thereof
abstract The invention relates to a stacked wafer structure and a packaging method thereof, belonging to the technical field of semiconductor chip packaging. It includes a wafer stack C2, a carrier wafer A1, an electrical connection layer (150), the wafer stack C2 is disposed above the carrier wafer A1 and connected by an electrical connection layer (150), the wafer stack C1 includes several layers of functional wafers. From bottom to top, the size of the wafer gradually decreases, and stepped sidewalls are formed around it. Above the carrier wafer A1, the front surface of the wafer stack C2 and its steps A dielectric layer III (300) is coated on the sidewalls of the shape of the dielectric layer, and an opening (301) of the dielectric layer III is formed, and a metal seed layer (310) and a metal bump (360) are arranged on the opening (301) of the dielectric layer III. , the metal bumps (360) are connected with the metal interconnect layer (120) of the adjacent wafer through the metal seed layer (310). The present invention provides a multi-layer stacked wafer structure and a manufacturing method thereof.
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priorityDate 2020-12-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 34.