| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f3518dca003902d9f332ad08ac9a6ffe |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7682
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14634
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-14636
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1469
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8234 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-146
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04N5-374
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04N5-369
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2019-06-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_89288bdb18d234ffdb71537c4d6012b6 |
| publicationDate |
2021-01-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-112219274-A |
| titleOfInvention |
Semiconductor device and manufacturing method of semiconductor device |
| abstract |
Provided is a semiconductor device that further reduces the inter-wiring capacitance of wirings arranged in an arbitrary layout. The semiconductor device (1) is provided with: a first inter-wiring insulating layer (120) provided on a substrate (100) and having a recess on the side opposite to the substrate; a first wiring layer (130) provided with Inside the concave portion of the first inter-wiring insulating layer; a sealing film (140) provided along the concavo-convex shape of the first wiring layer and the first inter-wiring insulating layer; the second inter-wiring insulating layer (220) , which is provided on the first inter-wiring insulating layer so as to cover the recessed portion, and has a flat surface opposite to the recessed portion; and a void (150), which is provided on the second inter-wiring insulating layer and the first wiring layer and the between the first inter-wiring insulating layers. |
| priorityDate |
2018-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |