http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112214158-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4ac7f95b9ae02e9a00ef92a3e12fc7f4 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7201 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7208 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7203 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-1016 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-30065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0835 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0652 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0658 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1668 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-1694 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0659 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-546 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F3-0679 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F3-06 |
| filingDate | 2019-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f4ea2c51606bbe1c9f2d333dc074017d |
| publicationDate | 2021-01-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-112214158-A |
| titleOfInvention | Executing device and method for host computer output and input command and computer readable storage medium |
| abstract | The invention relates to a method for executing host computer output and input commands, which is implemented by a processing unit of a device end loading and executing a program code of a first layer, and comprises the following steps: receiving a slot bit table from the second layer, comprising at least one record, each record associated with an input/output operation; receiving addresses of a plurality of callback functions from the second layer, wherein the callback functions are implemented to respond to a plurality of phases of the generic architecture of a plurality of types of host output-input commands; and iteratively executing a loop until the output-input operation in the slot bit table is processed, wherein, at each round in the loop, a callback function implemented in the second layer is called for a write operation or a read operation in the slot bit table. The multi-stage universal architecture is used for responding to various host output and input commands, so that the problems of difficult maintenance, large non-volatile storage space consumption and the like caused by using a plurality of sets of different firmware to respectively correspond to one host output and input command can be avoided. |
| priorityDate | 2019-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID2789 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID408137958 |
Total number of triples: 28.