http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112151616-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_079d992c41097c13960c9a57cb55f608 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66477 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0607 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0684 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 |
| filingDate | 2020-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_23769185789f72fdb2c52f5be91eb22c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9125eddc9d09c8e8aee95e6a472e78d5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2487a488b7366042be62874d5faabf4f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e377f3389c67c58c63d0ee0e8d005e5b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_19c3db2ed38eabfaafda15fa6ba16c28 |
| publicationDate | 2020-12-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-112151616-A |
| titleOfInvention | A kind of stacked MOS device and preparation method thereof |
| abstract | The present invention relates to a stacked MOS device and a preparation method thereof. A stacked MOS device includes a semiconductor substrate, and a plurality of PN structures are sequentially stacked on the surface of the semiconductor substrate from bottom to top; each of the PN structures includes: a silicon oxide layer disposed on the upper surface of the silicon oxide layer source region, drain region and channel region, the channel region is arranged between the source region and the drain region, and the boundary line between the channel region and the silicon oxide layer is lower than the source region and the The boundary line of the silicon oxide layer is also lower than the boundary line between the drain region and the silicon oxide layer; and the surface of the channel region of the PN structure at the top is sequentially provided with an insulating layer and a gate. The present invention increases the saturation current by increasing the number of conductive channels and specific structural design, and also reduces the leakage phenomenon. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114446793-A |
| priorityDate | 2020-08-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.