| abstract |
The invention discloses a multi-transmission mixed granularity reconfigurable array processor driven by data flow, and relates to the technical field of heterogeneous node design of reconfigurable arrays. The array processor includes a data access unit, a data storage unit, a coarse-grained processing unit, a fine-grained processing unit, a main core processor, a local memory and a task controller. The coarse-grained processing unit includes an input buffer, an output buffer, an arithmetic unit, a local register, a configurable register and a configurable data selector. The array processor improves the parallel execution capability of the reconfigurable array, reduces the intervention of the main core instruction, reduces the instruction fetching and translation overhead, and ensures the correctness of the calculation result by solidifying the functional operation code in the hardware. |