| abstract |
The present application generally relates to parallel processing devices. The parallel processing device may include multiple processing elements, a memory subsystem, and an interconnection system. The memory subsystem may include a plurality of memory slices, at least one of the plurality of memory slices being associated with one of the plurality of processing elements, and including a plurality of random access memory (RAM) tiles, each Each tile has separate read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnection system includes local interconnection and global interconnection. |