http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111949598-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9f65fb5f037d88e82f0060fa15296001 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-7807 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78 |
| filingDate | 2020-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_17c5afb1155ce827874e0bcf34443355 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a7a6a17acf0f0ccb3320cb6e4492b815 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6e41a251a267e64372c98a178138d4c8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5abbdf92eb00671eebf38f021faadd16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6904ad71d1e31c46266bb653f1e7fa40 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1f9fbedc45e6beec7a927714d0733cc5 |
| publicationDate | 2020-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-111949598-A |
| titleOfInvention | Multiplexing self-adaptation synchronizing circuit of system-on-chip pin |
| abstract | A multiplexing clock self-adaptive synchronous circuit of a system-on-chip pin comprises an automatic test device and a clock module, wherein the automatic test device is connected to a chip MCU to be tested through a single bus, an edge-picking circuit and a self-adaptive synchronous circuit are arranged in the chip MCU to be tested, and the edge-picking circuit is used for receiving START START pulses transmitted by the automatic test device, detecting and determining the pulse width and the baud rate of the pulses and transmitting the pulses to the self-adaptive synchronous circuit; the self-adaptive synchronous circuit receives the pulse width transmitted by the sampling edge circuit and determines the sampling interval of a subsequent bus; the invention avoids the use of an external clock and a corresponding PAD pin, can also ensure the communication between test equipment or an upper computer and the MCU of the chip to be tested under the condition of no calibration, and can avoid communication faults caused by clock precision deviation when used for a digital-analog mixed chip. |
| priorityDate | 2020-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426135032 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID7156993 |
Total number of triples: 20.