http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111755453-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f80f7502fa29eccce5d0ca3b654f4d96 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1157 |
| filingDate | 2020-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_780e98be9a3829b4290494e5b776ae55 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_997001fc236e7ed6551f1756597f96a8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3fafb29a1ae6794fdc4ad45a66e7ab57 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7f2a5730f525e535456375540dcab080 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_31bcec4607a92f56e621cc03a8a1ef8d |
| publicationDate | 2020-10-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-111755453-A |
| titleOfInvention | 3D memory device and method of manufacturing the same |
| abstract | A 3D memory device and a manufacturing method thereof are disclosed. The 3D memory device includes a substrate on which a doped well region is formed; a stack structure, located on a first surface of the substrate, the stack structure includes a plurality of gate conductors and a plurality of interlayer insulating layers stacked alternately; a plurality of channel pillars penetrating the stacked structure; a stop layer located between the bottom of the channel pillar and the doped well region of the substrate; and a plurality of through holes penetrating the substrate and extending from the second surface of the substrate, respectively To the bottom of each channel pillar, the through hole is filled with polysilicon, and the bottoms of the plurality of channel pillars form a common source connection through the polysilicon and the doped well region. In the memory device, a stop layer is added between the well region of the substrate and the stacked structure to ensure the etching depth of the channel column and the through hole, and the through hole filled with polysilicon is formed from the second surface of the substrate, so that the The channel pillar forms a common source connection through the well region and the polysilicon, which improves the erasing and programming speed of the memory, thereby improving the yield and reliability of the memory device. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113169184-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110828469-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112909001-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112909001-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11552092-B1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112768454-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112768454-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023279522-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110828469-A |
| priorityDate | 2020-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.