| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_eae3034a505868e4f55845e3e3667646 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45156
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-123
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F2203-45512
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-56 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-75
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-709
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F3-45475
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K4-502
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04N25-778
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03F3-45269
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K4-56 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04N5-378
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04N5-374 |
| filingDate |
2020-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7cdebb6df0e4d1574cee5b58e42a8095
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4d89c43ea7ce516ffdfa135bbdf85823
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08dcaa539723ec4e29189e4b238aabde
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d709419022686ce987f78324819f2c8c |
| publicationDate |
2020-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-111698439-A |
| titleOfInvention |
Integrating ramp circuit with reduced ramp settling time |
| abstract |
The present invention relates to integrating ramp circuits with reduced ramp settling time. The ramp generator includes an integrator including a first stage and a second stage, wherein the first stage has a first input and a second input, and a first output and a second output, and the second stage A first transistor and a second transistor are included that are coupled between the power rail and ground. The node between the first transistor and the second transistor is coupled to the output of the integrator amplifier. The control terminal of the first transistor is coupled to the first output of the first stage, and the control terminal of the second transistor is coupled to the second output of the first stage. During a ramp event in the ramp signal generated from the output, a first current flows from the output to ground. A trim circuit is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to the trim input. The second current substantially matches the first current. |
| priorityDate |
2019-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |