http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111508897-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c8fbf590463d3518a746d90a6a2c1c34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5e829b93e1bdf87272f2aaf3baaaa0f4 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0337 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32139 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823437 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate | 2019-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0ff97c65c08a37e5bde94db7e3d9e024 |
| publicationDate | 2020-08-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-111508897-A |
| titleOfInvention | Semiconductor device and method of forming the same |
| abstract | A semiconductor device and a method for forming the same, the method comprising: providing a substrate, the substrate comprising a first region, a second region and a third region arranged along a first direction; forming a plurality of fins arranged in parallel on the substrate, The extension direction of each fin is parallel to the first direction; a sacrificial gate structure and a plurality of gate structures are formed across a plurality of fins, the gate structure is located on the first and third regions of the substrate, and the gate structure is The extending direction is the second direction, and the sacrificial gate structure is located on the second area; a dielectric layer is formed on the substrate; a mask layer with a first opening and a second opening is formed on the dielectric layer, and the first opening is located in the second area The sacrificial gate structure is exposed on the top, and the second opening is located on the first region and the third region to expose part of the gate structure; using the mask layer as a mask, the sacrificial gate structure and the fins at the bottom of the first opening are etched. and a portion of the gate structure exposed by the second opening to form a first trench and a second trench respectively. The method improves the performance of the semiconductor device. |
| priorityDate | 2019-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.