| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-4824 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-499
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-4991
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06G7-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-501
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-57
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-3001
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06G7-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-49942 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-499
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06G7-60 |
| filingDate |
2018-11-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_53ad97106cbbe8f7f111014ce32151c3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_00493c8d5b956f1a1dbffaf60e57a6c7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21747acfb77b0d181ab4dff0d66658d4 |
| publicationDate |
2020-06-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-111344665-A |
| titleOfInvention |
Addition method, semiconductor device, and electronic equipment |
| abstract |
An addition circuit that suppresses overflow is provided. The adding circuit includes a first memory, a second memory, a third memory and a fourth memory. The addition operation includes the steps of: providing first data with a sign to a first memory; providing first data with a positive sign stored in the first memory to a second memory; providing a third memory with the first data stored in the second memory the first data with a negative sign; the first data with a positive sign stored in the second memory and the first data with a negative sign stored in the third memory are added to generate the second data; The second data is stored in the fourth memory. When all of the second data stored in the fourth memory are second data with a positive sign or both are second data with a negative sign, an addition operation is performed on all the second data stored in the fourth memory. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112214197-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112214197-A |
| priorityDate |
2017-11-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |