http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111291524-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_95d504eaa4db2a30d6e0578181afe15e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-42 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F30-39 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-42 |
| filingDate | 2020-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7ed13da2510d1118a3e4b83df2d62a15 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5a5e941e82084d8bf7b7b9f4835d2231 |
| publicationDate | 2020-06-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-111291524-A |
| titleOfInvention | A structure and method for realizing AXI bus crossing clock domain |
| abstract | The present invention provides a structure and method for realizing AXI bus cross-clock domain. The module includes a function channel signal buffer FIFO unit, a master clock function channel signal serial-to-parallel conversion unit, a slave clock function channel signal serial-to-parallel conversion unit, a master control logic unit and a slave control logic unit; method: the master module uses the master clock to the master-slave direction. AXI bus function channel sub-module write signal; the master module write signal is merged by the master clock function channel signal merging subunit, and then buffered by the master clock function channel signal buffer FIFO unit, and provided to the slave clock function channel signal splitting subunit Perform splitting; the slave module reads the signal split from the clock function channel signal splitting subunit to the AXI bus function channel submodule autonomously from the slave clock. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112306924-A |
| priorityDate | 2020-01-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 25.