| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-324
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02337
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02211
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02343
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76224
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76229
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate |
2019-11-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d3e89abcef0f81914af8a35c20080b96
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1fa32f293c1722048618ae748be44aa2 |
| publicationDate |
2020-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-111211089-A |
| titleOfInvention |
Integrated circuit structure and method of making the same |
| abstract |
The present disclosure relates to integrated circuit structures and methods of fabricating the same. An integrated circuit structure includes: a bulk semiconductor region; a first semiconductor strip above and connected to the bulk semiconductor region; and a dielectric layer including silicon oxide. Doping silicon oxide with carbon atoms. The dielectric layer includes a horizontal portion over and in contact with the top surface of the bulk semiconductor region, and a vertical portion connected to one end of the horizontal portion. The vertical portion is in contact with the sidewall of the lower portion of the first semiconductor strip. The tops of the first semiconductor strips protrude above the top surfaces of the vertical portions to form semiconductor fins. The horizontal and vertical sections have the same thickness. The gate stack extends over the sidewalls and top surface of the semiconductor fin. |
| priorityDate |
2018-11-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |