http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111130511-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ca46be4e68fa1f5a8b2ef4ab654c490a |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-249 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-24 |
| filingDate | 2018-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8cf032d1bd1f73901f0cf7250efb7602 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2b05144a54d059518aca28f99d98ce7e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f393843c0775c54e3f0ed50fec53f695 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7eee2de035a508841b1f56cb2609f4d8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3b88b846687b5c59f5319a06e33d7b3c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5f861f3aa844733cd3eb773be571aa0e |
| publicationDate | 2020-05-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-111130511-A |
| titleOfInvention | An all-digital low-voltage low-power clock-controlled voltage comparator |
| abstract | The invention relates to an all-digital low-voltage low-power clock-controlled voltage comparator, comprising: an inverter, a delay line, a power input terminal, a ground terminal, a clock signal terminal, a non-inverting voltage input terminal, an inverting voltage input terminal, a non-inverting voltage input terminal, and a non-inverting voltage input terminal. an output terminal and an inverting voltage output terminal; wherein, the clock signal terminal is respectively connected with the inverter and the delay line, and the delay line is respectively connected with the in-phase voltage input terminal and the inverting voltage input terminal The power input terminal is respectively connected to the inverter and the delay line, and the ground terminal is respectively connected to the inverter and the delay line. The all-digital low-voltage and low-power clock-controlled voltage comparator can not only alleviate the design difficulties of conventional clock-controlled voltage comparators, but also improve the circuit performance by making full use of the advantages of advanced nanotechnology. |
| priorityDate | 2018-10-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 61.