| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_786a55964f0623938e701b4510cacfff |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02P80-30 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3121
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3135
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-538
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5386
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-4824
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-538
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-28 |
| filingDate |
2019-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_79497a1ba0198f0b343c56e73545d547
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2116cdd1d3b6120f303a7d550f6236f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d4adfbf2d4127b1a09873f57582f543f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ae151aa1a81f7040c7b598ba7285bd5d |
| publicationDate |
2020-04-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-110957302-A |
| titleOfInvention |
Transistor with shielding structure, packaging device and manufacturing method thereof |
| abstract |
A transistor includes a semiconductor substrate having an active device region formed therein and an interconnect structure on a first surface of the semiconductor substrate. The interconnect structure is formed from multiple layers of dielectric materials and conductive materials. A drain runner and a gate runner are formed in the interconnect structure. A shield structure extends over the second surface of the interconnect structure, the shield structure being positioned between the drain runner and the gate runner. |
| priorityDate |
2018-09-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |