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filingDate 2018-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a0bc430a634547b48518f20019157e1a
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publicationDate 2020-02-07-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-110771043-A
titleOfInvention Timing Controller for Dead Time Control
abstract Systems, methods and apparatus are described for biasing and driving high voltage semiconductor devices (T1, T2) using only low voltage transistors (internal to 410). The apparatus (410) and method are adapted to control a plurality of high voltage semiconductor devices (T1, T2) to achieve high voltage power control, eg, power amplifiers, power management and conversion (eg, DC/DC) and a first voltage (V IN ) and a The maximum voltage handling (Vdd1, Vdd2) of the low voltage control transistors is larger compared to other applications. According to one aspect, the edges of the control signal (IN) to the high voltage semiconductor devices (T1, T2) are provided by a basic edge delay circuit (FIG. 4: 215 interior; FIG. 14a: 1410) comprising transistors, current sources and capacitors (FIG. 4 : 215; Fig. 14a: 1410) timing control. Inverters may be selectively coupled to the input and/or output of the base edge delay circuit via switches to allow timing control of the rising or falling edge of the control signal.
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http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112968611-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111404526-A
priorityDate 2017-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 53.