http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110729248-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0669 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0928 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 2019-10-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-09-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2021-09-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-110729248-B |
| titleOfInvention | Preparation method of stacked nanowire or chip CMOS (complementary Metal oxide semiconductor) device |
| abstract | The invention discloses a method for preparing a stacked nanowire or chip CMOS device, which comprises the following steps: providing a semiconductor substrate which comprises an N well region and a P well region; preparing a nanowire or sheet channel on a semiconductor substrate; forming a grid dielectric layer on the nanowire or the sheet channel, and sequentially forming a first metal layer, a second metal layer and a third metal layer on the grid dielectric layers of the N well region and the P well region; removing the first metal gate formed by the P well region and the third metal layer formed on the gate dielectric layer of the N well region at a high selection ratio; sequentially forming a fourth metal layer, a fifth metal layer and a sixth metal layer on the second metal layer of the N well region and the gate dielectric layer of the P well region; depositing a seventh metal layer on the sixth metal layer; the filling of the gate dielectric layer and the first metal gate or the second metal gate can be completed in a smaller range; and the first metal grid and the second metal grid are made of different materials, so that the requirements of different properties of NMOS and PMOS devices can be met. |
| priorityDate | 2019-10-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.