http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110581167-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_74552913c0e72e4f9b6a3913107d7f7c |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0684 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-205 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7371 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-737 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-331 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-205 |
| filingDate | 2019-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d0bdccb35918fc58184fea352ebc746 |
| publicationDate | 2019-12-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-110581167-A |
| titleOfInvention | Mesa AlGaN/GaN heterojunction bipolar transistor device and preparation method thereof |
| abstract | The invention provides a mesa AlGaN/GaN heterojunction bipolar transistor device, which comprises Al 2 O 3 a substrate sequentially laminated on Al 2 O 3 A first intrinsic GaN buffer layer, a second intrinsic GaN buffer layer, a GaN substrate layer, a GaN collector region, a GaN sub-collector region, a first intrinsic GaN barrier layer, a GaN base region thin layer, a second intrinsic GaN barrier layer, and Al on the substrate x Ga 1‑x N layer, Al r Ga 1‑r The GaN sub-collector region is etched from the GaN cap layer to form a left trapezoid table top and a right trapezoid table top, and a specific region of the left trapezoid table topPhosphorus ion implantation is performed, boron fluoride ion implantation is performed in a specific area of the right trapezoid table top, an oxide film layer is formed on the surface of the whole device, a corresponding electrode window is etched on the oxide film layer corresponding to the electrode contact hole, a polycrystalline silicon layer is formed on the corresponding electrode window, and an electrode lead is formed at the position of the corresponding electrode window. The invention also provides a preparation method of the device. The method can improve the reliability, the characteristic frequency and the breakdown voltage of the device, and the preparation method can be compatible with the main flow compound semiconductor process. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112993033-A |
| priorityDate | 2019-10-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.