http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110211924-B

Outgoing Links

Predicate Object
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76805
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
filingDate 2019-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2021-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2021-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-110211924-B
titleOfInvention Method for manufacturing wafer structure
abstract The application provides a manufacturing method of a wafer structure, after a first wafer and a second wafer are bonded, etching can be carried out from a first substrate of the first wafer to form a silicon through hole, then deposition of an insulating layer is carried out, the thickness of the insulating layer at the opening corner of the silicon through hole is larger than the thickness of the insulating layer on the side wall and the bottom surface of the silicon through hole, then anisotropic etching of the insulating layer is carried out until the insulating layer on the bottom surface of the silicon through hole is removed, and then filling of the silicon through hole is carried out. The insulating layer in the through silicon via plays a role in isolating and protecting a device, the thickness of the insulating layer at the opening corner of the through silicon via is larger than the thickness of the insulating layer on the side wall and the bottom surface of the through silicon via, and in the subsequent process of removing the insulating layer on the bottom surface of the through silicon via, even if the insulating layer at the opening corner of the through silicon via is lost, the thickness of the insulating layer is not too thin, so that the reliability of the insulating layer in the through silicon via is improved, and the influence of the forming process of the through silicon via on the yield and the performance of the device is.
priorityDate 2019-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

Predicate Subject
isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID5461123
http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419559541

Total number of triples: 15.