| Predicate |
Object |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02516
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02381
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02576
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0245
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78603
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02579 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-762
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02 |
| filingDate |
2017-10-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2022-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2022-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-110178211-B |
| titleOfInvention |
High-resistivity silicon-on-insulator substrate with enhanced charge-trapping efficiency |
| abstract |
The present invention provides a multilayer semiconductor-on-insulator structure in which the handle substrate and the epitaxial layer interfacially contacting the handle substrate include opposite types of electrically active dopants. The epitaxial layer is free carrier depleted by the handling substrate, thereby resulting in a high apparent resistivity, which improves the function of structures in RF devices. |
| priorityDate |
2016-10-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |