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filingDate 2019-03-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2bfc7e751731e237f72e07ee351ac92c
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publicationDate 2019-07-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-110047842-A
titleOfInvention A silicon-based charge trapping memory device and preparation method thereof
abstract A silicon-based charge trapping type storage device, on a p-Si substrate, are: SiO 2 transition layer, tunneling layer, charge trapping medium layer, blocking layer (medium), gate electrode, and the substrate is also provided with a substrate electrode; a layer of SiO 2 transition layer is added between the substrate Si and the tunneling layer dielectric Al 2 O 3 ; the thickness of the SiO 2 transition layer is 0.1-2.5 nm; the thickness of the SiO 2 transition layer and the thickness of the tunneling dielectric Al 2 O 3 The sum is 2 to 6 nm. The SiO2 preparation method uses a thermal oxidation method. The lower electron state density between the SiO 2 transition layer and the Si substrate can reduce the interface state density at the Si/Al 2 O 3 interface, thereby improving the reliability of the silicon-based charge trapping memory device.
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Total number of triples: 32.