http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110034067-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823892 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-8232 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8232 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8238 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092 |
| filingDate | 2018-01-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-01-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2021-01-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-110034067-B |
| titleOfInvention | Semiconductor device and method of forming the same |
| abstract | A semiconductor device and method of forming the same, the method comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises a TFET region and a CMOS region; covering the TFET region by using a first covering layer, forming a CMOS lightly doped drain region in the CMOS region under the protection of the first covering layer, and carrying out first annealing process treatment; removing the first covering layer to form a TFET grid side wall and a CMOS grid side wall; forming source and drain doped regions in the TFET region and the CMOS region, and carrying out second annealing process treatment; forming a protective layer covering the CMOS area, removing at least one part of the TFET grid side wall under the protection of the protective layer, and exposing the semiconductor substrate between the TFET grid and a source drain doped area of the TFET area; and forming a TFET lightly doped drain region in the TFET region. The scheme of the invention can improve the concentration gradient of the TFET lightly doped drain region junction surface, and improve the tunneling probability and the on-state current of the device. |
| priorityDate | 2018-01-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.