| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82345
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-82385
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0924
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0922
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823842
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42376
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-772
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-092
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 |
| filingDate |
2018-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2efeb5a24d26b4caf84d05e4a170fd70
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d0388c3e633a348b5bb357dafed39e43
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ecbff316a1d69484d97d132b0612d244
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_80ba302cb6c5c46e2be0b6064ab47bfe
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_58a9fcb2e7b4a94368f2b58ea72eece5 |
| publicationDate |
2019-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-109830479-A |
| titleOfInvention |
Semiconductor devices with transistors with different work function layers |
| abstract |
A semiconductor device may include a substrate having a first region and a second region. The first transistor may be in the first region and include a first gate line including a first lower metal-containing layer and a first upper metal-containing layer on the first lower metal-containing layer. The second transistor may be in the second region and include a second gate line having a width equal to that of the first gate line and including a second lower metal-containing layer and a second lower metal-containing layer A second upper metal-containing layer on the layer. Each of the uppermost end of the first upper metal-containing layer and the uppermost end of the second lower metal-containing layer may be at a higher level than the uppermost end of the first lower metal-containing layer. |
| priorityDate |
2017-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |