| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0886
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66484
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7854
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2018-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7c060f05cb35101de1a986060eb8d038
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_96880f22093c62554655633d599fdce6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c10d4e75174f8bf97fec17225bb4d255
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c53a56fb08cc9996fa1a88142f4ceb5 |
| publicationDate |
2019-04-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-109585551-A |
| titleOfInvention |
Semiconductor structure and method of making the same |
| abstract |
The invention discloses a semiconductor structure and a manufacturing method thereof. An asymmetric critical multi-pitch layout of semiconductor structures with different gate pitches to alleviate parasitic capacitances between gates, thereby improving cut-off frequency. The semiconductor structure may include fins on the substrate. The semiconductor structure may also include a first gate structure and a second gate structure formed on the fin and separated by a first spacer. The semiconductor structure may also include a third gate structure formed on the fin between the first gate structure and the second gate structure. The third gate structure may be spaced apart from the first gate structure by a second space and spaced apart from the second gate structure by a third space greater than the second space. The semiconductor structure also includes a source region formed between the first gate structure and the third gate structure and a drain region formed between the third gate structure and the second gate structure. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11526649-B2 |
| priorityDate |
2017-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |