http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109522753-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-79 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2013-0057 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2013-0054 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2221-2103 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C27-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G09C1-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-72 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0028 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0026 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F21-75 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L9-3278 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0059 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-72 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F21-75 |
| filingDate | 2017-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2020-11-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-109522753-B |
| titleOfInvention | Circuit structure and driving method thereof, chip and authentication method thereof, and electronic device |
| abstract | A circuit structure for realizing a physical unclonable function, a driving method thereof, an integrated circuit chip and an authentication method thereof, and an electronic device. The circuit structure includes a multi-layer circuit, a first address circuit and an output circuit. The multi-layer circuit includes an addressable first resistive switching device array and an addressable second resistive switching device array, and the first address circuit is configured to map the resistance values of the second resistive switching devices in the second resistive switching device array It becomes the first address, and the first address is used to locate the selected first resistive switching device; the output circuit is configured to acquire and process the resistance value of the selected first resistive switching device, and output the processing result. The circuit structure is based on a multi-layer resistive memory array to achieve a physical unclonable function, and the resistive device arrays of each layer are connected by address mapping, which improves the data complexity, improves the ability of the physical unclonable function to resist machine learning algorithm attacks, and increases hardware. Certified security. |
| priorityDate | 2017-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.