| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-231
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66825
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8828
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-8825
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-841
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-01
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N50-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B69-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-011
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B61-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-235
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-245 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00 |
| filingDate |
2018-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f25b6a3d538d72c10847feeb75c0fa6b
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d2fc6e5923528e55cf822774cdb4eff |
| publicationDate |
2019-03-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-109427842-A |
| titleOfInvention |
Semiconductor devices and electronic systems with memory structures, and related methods |
| abstract |
The present application relates to semiconductor devices and electronic systems having memory structures and related methods. A semiconductor device includes a memory cell, a first dielectric liner material overlying a side surface of the memory cell, a high-k dielectric material overlying the side surface of the first dielectric liner material, a cover A second dielectric liner material on the side surfaces of the high-k dielectric material and additional dielectric material overlying the side surfaces of the second dielectric liner material. An electronic system and a method of forming a memory structure are also described. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113611658-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114631198-A |
| priorityDate |
2017-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |