| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2029-7858
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02579
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02576
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0262 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-6656
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66621
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823821
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31051
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7846
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7855
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-41791
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823431
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7833 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate |
2017-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4747b049a97b36dffa93027800b1291c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e7f0aff1df79eb205a01d34f5aecf1a5
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6eeecad5ae9c2690f6768e0754618f3f |
| publicationDate |
2019-03-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-109427671-A |
| titleOfInvention |
Fin structures for semiconductor devices |
| abstract |
A method of forming first and second field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are substantially equal to each other. The method also includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure, and depositing a dielectric layer over the modified first and second fin structures . The method also includes forming a polysilicon structure on the dielectric layer and selectively forming spacers on sidewalls of the polysilicon structure. Embodiments of the invention also relate to fin structures for semiconductor devices. |
| priorityDate |
2017-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |