| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1047 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31144
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76804
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02216
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0276
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76879
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02274
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5328
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76811
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76813
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76801
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2018-08-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2021-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-109427660-B |
| titleOfInvention |
Semiconductor device and method of manufacturing the same |
| abstract |
A porous dielectric layer is formed over the substrate, an anti-reflection layer is formed over the porous dielectric layer; and a first hard mask is formed over the anti-reflection layer. Via openings and trench openings are formed within the porous dielectric layer using the antireflective layer and the first hardmask as mask materials. After forming the trench openings and the via openings, the first hard mask is removed. An interconnect is formed within the opening and has a profile angle between about 70° and about 80° and a depth ratio between about 65% and about 70%. Embodiments of the present invention relate to semiconductor devices and methods of fabricating the same. |
| priorityDate |
2017-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |