| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_82a9e22a923eca64a02a97f0dfb493ed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17744 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17744
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-17736
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K19-00361
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-177 |
| filingDate |
2017-04-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_aceaaa20cc0c6fad70dd79e7d15bf1e7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_04926ff0eb438dd1189a8ca725e633c1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_51bf4aeb64ed1bd65a8c309ef9b05fa0
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f973b3a8d3d691a7d8d92cd3957ceec9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e3d7c28accb89b29286b84fee19a95f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9597d16e7c57f044b98f126558f731bc |
| publicationDate |
2019-02-05-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-109314098-A |
| titleOfInvention |
Standard cell architecture to reduce parasitic resistance and increase data path speed |
| abstract |
A MOS device may include a first logic component having a first input on a second trace and a first output on a third trace. The MOS device may include a second logic component having a second input on the fourth trace and a second output on the fifth trace. For example, the MOS device includes a first interconnect on the Mx layer coupled to a first input on the second trace. In another example, the MOS device includes a second interconnect on the Mx layer coupled to the first output on the third trace. The MOS device includes a third interconnect on the My layer coupled to the second input on the fourth trace. Still further, the MOS device includes a fourth interconnect on the My layer coupled to the second output on the fifth trace. |
| priorityDate |
2016-06-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |