http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109280946-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_64a942a6e513e5ca33a708f3cb665c4c |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D3-48 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/C25D7-12 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D3-48 |
| filingDate | 2018-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_93dca0dd7117760fc3697e6a4e55f7b3 |
| publicationDate | 2019-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-109280946-A |
| titleOfInvention | A kind of folded electroplating surface gold process of high-voltage diode silicon |
| abstract | The present invention relates to a kind of high-voltage diode silicon to fold electroplating surface gold process.It is closed cleaning agent liquid bath first；It is closed this plating bath heater power source；It is closed electroplating source；By special fixture on gold silicon closed assembly to be plated；Degreasing washing；Pickling；Washing；Preplating: fixture is placed in preplating liquid bath, and 25s is electroplated；Control electroplating power supply voltage is 3.35 ± 0.01V；This plating: confirm that this plating solution tank liquor temperature is 60~65 DEG C, fixture is placed in this coating bath, 2.0 ± 0.5min of this plating, adjustment electroplating power supply electric current is 0.6 ± 0.1A, and electroplating voltage is indefinite；Post-processing；Dehydration and drying.Advantage is that simple process is perfect, and the silicon after an alloy is folded to plate a thin layer of layer gold using electric plating method, and alloy wellability is good between gold and slicker solder weld tabs, can effectively improve weld strength after secondary welding；It is smooth uniform that the folded secondary alloy rear surface of gold silicon is electroplated；Assembling sintering qualification rate after gold-plated then reaches 99.2%. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112030207-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113319036-A |
| priorityDate | 2018-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 37.