| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_323834c4243d986e53b08d8849f9664e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1066 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-402
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-2003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-205 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-778
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-772
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-02 |
| filingDate |
2017-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5176010ea3a1f1bd59391388651254cf
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a01eff1796f1684a3f411da8ab083043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0f2f75b2e299d444a367edf14fc1ed36
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f08e9ef0f6b119fda2432d44e0ad12bb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_37e094bcef6912bfbb02ad66990df35a |
| publicationDate |
2019-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-109196650-A |
| titleOfInvention |
Multi-step surface passivation structure and manufacturing method thereof |
| abstract |
A gallium nitride (GaN) transistor includes two or more insulating semiconductor interface regions (insulating regions). A first insulating region disposed between (near the gate) gate and drain minimizes gate leakage current and fields near the gate, which result in high gate-drain charge (Qgd). A second insulating region (or regions) disposed between the first insulating region and the drain minimizes the electric field at the drain contact and provides a high density of charge in the channel for low on-resistance. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111180528-A |
| priorityDate |
2016-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |