http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-109002159-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3243 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-3234 |
| filingDate | 2018-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-12-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2020-12-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-109002159-B |
| titleOfInvention | CPU state control circuit and method |
| abstract | The invention provides a CPU state control circuit and method. The state control circuit of the CPU comprises a register and a register modification circuit; the register stores a free flag bit; and the register modification circuit is used for modifying a plurality of setting zone bits corresponding to the CPU in the register according to a setting sequence when the idle zone bit is effective. The response speed of the state control circuit for controlling the CPU state is faster than that of the state control circuit for controlling the CPU state by software. |
| priorityDate | 2018-06-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.