http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108878361-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate | 2018-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2021-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-108878361-B |
| titleOfInvention | Semiconductor device and method for manufacturing the same |
| abstract | The invention provides a semiconductor device and a manufacturing method thereof, the manufacturing method comprises the steps of taking a first patterning mask layer as a mask, etching and removing a part of thickness of a semiconductor substrate in a first device area to form a groove, then forming a first gate oxide layer with the top surface lower than that of the semiconductor substrate in a second device area in the groove, then forming a second gate oxide layer on the surface of the semiconductor substrate in the second device area, and then leveling the top surfaces of the polycrystalline silicon layers of the first device area and the second device area through deposition and top surface planarization of the polycrystalline silicon layers. The method of the invention is suitable for manufacturing various integrated circuits with different device areas needing different polysilicon thicknesses. |
| priorityDate | 2018-06-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 17.