| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_543f81076a0539dda3718ef97249ec66
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_88fc7f9eb617072238851d46591a0c76 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-30
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66666
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0649
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-053 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11568 |
| filingDate |
2017-05-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0abf1ad06fbc475a3e841c0b2227c9d6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b6d8dff2160c742ecb15b6c113c06606
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_14d19f00160b2b8f2906a04356bfed9a |
| publicationDate |
2018-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-108807414-A |
| titleOfInvention |
Semiconductor element and manufacturing method thereof |
| abstract |
The invention discloses a semiconductor element and a manufacturing method thereof. The method for manufacturing a semiconductor element includes firstly forming a first groove in a substrate, then forming a first shallow trench isolation in the first groove and simultaneously forming a second groove beside the first groove, wherein The shallow trench isolation includes an upper half and a lower half, and the upper surface of the upper half is aligned with or higher than the lower surface of the second groove, and then a conductive layer is formed in the first groove and the second groove to form the second groove. A gate structure and a second gate structure. |
| priorityDate |
2017-05-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |