http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108807392-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-30 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11521 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11517 |
| filingDate | 2018-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2020-12-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-108807392-B |
| titleOfInvention | Flash memory and method of making the same |
| abstract | The present invention provides a flash memory and a manufacturing method thereof. In the manufacturing method, before etching the floating gate layer in the opening, the floating gate layer in the opening is doped with a barrier impurity, and the doping The impurity barrier impurities extend into the floating gate layer under the part of the bottom of the first sidewall spacer, so as to divide the floating gate layer into a barrier-doped floating gate layer and a non-barrier-doped floating gate layer, and further A floating gate including a non-barrier-doped floating gate layer and a barrier-doped floating gate layer may be formed subsequently, and the non-barrier-doped floating gate layer and the barrier-doped floating gate in the floating gate layer can form a self-built barrier, which can be used to improve the floating gate and the source subsequently filled in the opening even if the formed second spacer has a thinner coverage on the floating gate sidewall The isolation performance between the lines of polysilicon can therefore improve the data retention capability of the flash memory. |
| priorityDate | 2018-06-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.