http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108650136-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L67-1095 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L41-0803 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L67-568 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L12-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H04L41-12 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L29-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L12-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H04L12-24 |
| filingDate | 2018-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2020-10-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-108650136-B |
| titleOfInvention | Design method of master/slave station card for realizing Powerlink industrial real-time Ethernet communication |
| abstract | The invention discloses a design method of a master/slave station card for realizing Powerlink industrial real-time Ethernet communication. The master-slave/station card can be configured as a Powerlink industrial real-time Ethernet communication master station card or a slave station card. When the master/slave station card is designed, an on-chip CPU, a Powerlink industrial real-time Ethernet communication IP core and a software interface for realizing communication between the on-chip CPU and the IP core are constructed in the FPGA. The on-chip CPU comprises a Powerlink protocol stack user layer, and the IP core comprises a kernel layer and an MAC layer of the Powerlink protocol stack. When the master/slave station card is used, a gold finger is inserted into a CAL female seat of a mainboard of an upper computer, the upper computer runs a Powerlink protocol stack application program, and the FPGA runs a user layer, a kernel layer and an MAC layer. The minimum cycle period reaches 1ms and the synchronous response time reaches 480us under a non-real-time operating system such as Windows; under the condition of no operating system, the minimum cycle period can reach 200us, and the jitter is about 1 us. |
| priorityDate | 2018-05-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.