http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108630254-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-106 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1087 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1057 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5621 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5671 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1084 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate | 2018-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2022-12-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-108630254-B |
| titleOfInvention | Non-volatile memory device providing reduced data line loading |
| abstract | A nonvolatile memory device according to some embodiments of the inventive concepts may include: a memory cell array, a first page buffer connected to the memory cell array via a first plurality of bit lines, and a second plurality of bit lines via a second plurality of bit lines. A line is connected to a second page buffer of the memory cell array. The first page buffer circuit may include a first bit line selection circuit, a first bit line cutoff circuit, and a first latch circuit. The second page buffer may include a second bit line selection circuit, a second bit line cutoff circuit, and a second latch circuit. The first and second bit line selection circuits, the first and second bit line cutoff circuits, and the first and second latch circuits may be sequentially arranged in a direction away from the memory cell array. The width of the data line may be greater than that of the bit line. |
| priorityDate | 2017-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID31170 http://rdf.ncbi.nlm.nih.gov/pubchem/gene/GID149840 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419557764 |
Total number of triples: 27.