http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108573912-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1005 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76835 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-532 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2017-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2021-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2021-02-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-108573912-B |
| titleOfInvention | Semiconductor structure and forming method thereof |
| abstract | A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein an interlayer dielectric layer and an interlayer interconnection structure penetrating through the interlayer dielectric layer are formed in the substrate; forming an upper dielectric layer of a laminated structure on the substrate, wherein the upper dielectric layer comprises a plasma enhanced silicon oxide layer; etching the upper dielectric layer to form an opening exposing the interlayer interconnection structure; and filling the opening with a conductive material to form an upper-layer interconnection structure electrically connected with the interlayer interconnection structure. Compared with the upper dielectric layer with a single-layer structure made of plasma enhanced silicon oxide, the upper dielectric layer with the laminated structure has smaller stress on the adjacent interlayer dielectric layers, so that the probability of time-lapse breakdown of the adjacent interlayer dielectric layers can be reduced, the breakdown voltage of the adjacent interlayer dielectric layers can be increased, the probability of splitting between the upper dielectric layer and the adjacent interlayer dielectric layers can be reduced, the chip packaging interaction can be improved, and the reliability of the formed semiconductor structure can be improved. |
| priorityDate | 2017-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 25.