Predicate |
Object |
assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f80f7502fa29eccce5d0ca3b654f4d96 |
classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40114 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-20 |
classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11551 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11578 |
filingDate |
2018-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_67739d9067dde91bb88d49b7bf4f870b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c8723601d7f57baface78bb4c7c9f886 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a9b539a4be6579acf1e34a1a5ca6fb8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_80eaf6be72aa3592b324b8ee75ab48be http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ebc61fe7091c0d33ac0a93d1b94061df http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3e7cda560126ab0a072e85aba795588d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f048f83a6eeaa915e05e2cee2bf04da1 |
publicationDate |
2018-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber |
CN-108550578-A |
titleOfInvention |
Three-dimensional memory manufacturing method |
abstract |
The invention discloses a method for manufacturing a three-dimensional memory, comprising: forming a dielectric layer stack consisting of multiple first dielectric layers and multiple second dielectric layers alternately arranged on a substrate; etching the dielectric layer stack to form a plurality of channel regions; between the channel regions, etching the dielectric layer stack to form trenches exposing the substrate; and performing lateral etching such that curvature of sidewalls of the trenches is at least partially reduced. According to the three-dimensional memory manufacturing method of the present invention, additional lateral etching is added after the contact groove is etched to make the side wall of the groove straight, thereby improving device reliability. |
isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-112490250-A |
priorityDate |
2018-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type |
http://data.epo.org/linked-data/def/patent/Publication |