| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_67341f7dcb76f9c91cdcc5e7f867a01d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-00014
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-14181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-1132
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-11849
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13111 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-14
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-488
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-742
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-31 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-488 |
| filingDate |
2018-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a137ddd6d59b90401f8f3470d2defa3c
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e359d1cfb671cf58eb51c7b4ddbd2cc7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_af4892d0afa1dc4c7b461cd71fd84afb
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e918e343bbd6b142ebba1397dcac4ded |
| publicationDate |
2018-08-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-108447831-A |
| titleOfInvention |
A kind of double-sided circuit die design and packaging method |
| abstract |
The present invention relates to a kind of double-sided circuit die design and packaging methods.It the described method comprises the following steps：Wafer is designed and is made according to double-sided circuit；Breakover element is installed in side, and encapsulates wafer and support plate.Double-sided circuit die design of the present invention and packaging method are applied to semiconductor chip process, half design area can be reduced, to which cost of material be greatly lowered；Interference is effectively isolated between circuit during effectively single side can be designed；Can will encapsulation patch be reduced to bonding wire twice technological process together with side dress flow, and encapsulation Heraeus and bonding wire materials'use are saved, to reduce processing cost again；Side fills weldability and is higher than traditional bonding wire weldability, to which effective retention property is stablized. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2019179060-A1 |
| priorityDate |
2018-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |