http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108257861-B
Outgoing Links
Predicate | Object |
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classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-283 |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-283 |
filingDate | 2016-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate | 2021-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationDate | 2021-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | CN-108257861-B |
titleOfInvention | Preparation method of gate oxide layer and MOS power device |
abstract | The invention provides a preparation method of a gate oxide layer and an MOS power device, wherein the preparation method comprises the steps of carrying out high-temperature sacrificial oxidation on a silicon carbide epitaxial wafer with a first conductive type, and forming a sacrificial oxide layer on the upper surface of the epitaxial wafer; corroding the sacrificial oxide layer until the sacrificial oxide layer on the epitaxial layer is completely removed; performing high-temperature surfacing treatment on the upper surface of the epitaxial layer after the sacrificial oxide layer is removed to form a smooth passivated surface; and (3) sequentially carrying out high-temperature dry oxygen oxidation and oxidation under a phosphorus atmosphere on the silicon carbide epitaxial wafer, and then annealing to form a gate oxide layer on the smooth passivated surface. Compared with the prior art, the preparation method of the gate oxide and the MOS power device provided by the invention can reduce SiC/SiO 2 Interface defects at the interface due to impurities and/or surface lattice defects. |
priorityDate | 2016-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.