| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c63bc5ef3ae590b0603de4587961cac3 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2254
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2272 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1087
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1039
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03L7-0814
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-106 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076 |
| filingDate |
2017-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ad0dc7a857300d47be2b30049a057a4d |
| publicationDate |
2018-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-108231111-A |
| titleOfInvention |
Semiconductor devices |
| abstract |
A kind of semiconductor devices includes phase-comparison circuit, circuit, data input/output (I/O) circuit occur for output enable signal.The phase of clock signal and the phase of delay lock loop (DLL) clock signal are compared by phase-comparison circuit, to generate phase information signal.Output enable signal occurs circuit and carrys out latching internal order in response to the first pre-control signal and export the internal command of latch for output enable signal in response to operation clock signal and the second pre-control signal.Output enable signal occurs circuit and generates the first pre-control signal according to internal clock signal and input clock signal.Data I/O circuits receive input data and are the output data synchronous with gating signal by the input data received output in response to output enable signal. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111145808-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111161772-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111435601-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111145808-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111435601-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110853689-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110853689-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111934655-A |
| priorityDate |
2016-12-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |