| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0217
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02178
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02167
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76883 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-31111
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76834
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76832
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53257
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76885
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53209
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2017-11-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2021-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-108122833-B |
| titleOfInvention |
Method for fabricating semiconductor device |
| abstract |
A self-aligned via and method of fabricating a semiconductor device utilizing a self-aligned process constrained by a double trench to form the via. The method includes forming a first trench and depositing a first metal in the first trench. Thereafter, the process includes depositing a dielectric layer over the first metal such that a top surface of the dielectric layer is at substantially the same level as a top surface of the first trench. Next, a second trench is formed and a via is formed by etching a portion of the dielectric layer exposed by an overlap region between the first trench and the second trench. The via exposes a portion of the first metal and a second metal is deposited in the second trench such that the second metal is electrically coupled to the first metal. |
| priorityDate |
2016-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |