| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-3065 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02532
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78618
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0669
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78651
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-4966
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-30604
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66484
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7831
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823456
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02236
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02603
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28123
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66537
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate |
2017-10-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2020-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2020-09-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-108122774-B |
| titleOfInvention |
Semiconductor structure and method of forming a semiconductor device |
| abstract |
The semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first semiconductor layer and the second semiconductor layer have different material compositions. A dummy gate stack is formed over the uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed under the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the void. Embodiments of the present invention also relate to threshold voltage adjustment for a gate all around semiconductor structure. |
| priorityDate |
2016-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |