| Predicate |
Object |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0069
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-79
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2213-71
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0007 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-004
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-003
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-063
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-823
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-826
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0097
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-845
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B63-84
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C13-0069 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C13-00 |
| filingDate |
2017-08-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate |
2021-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate |
2021-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-108122577-B |
| titleOfInvention |
semiconductor memory device |
| abstract |
According to one embodiment, a semiconductor memory device includes: a first insulating layer; global bit lines and reference bit lines provided on the first insulating layer; a second insulating layer provided on the global bit lines and the reference bit line; a select gate line provided on the second insulating layer; a first transistor provided on the global bit line; a local bit line coupled to the first transistor; first and second memory cells; and a sense amplifier. The global bit line and the reference bit line three-dimensionally intersect the select gate line via the second insulating layer. |
| priorityDate |
2016-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |