| abstract |
A semiconductor memory device according to one embodiment includes a row decoder and a memory cell array including a first functional block. The first functional block has: the first area (CEL); the second area (WLHU), adjacent to the first area (CEL) in the first direction (Y direction); and the third area (CNCT), connected to the first Area (CEL) and Area 2 (WLHU). The memory cell array also includes: a first insulating layer (730), which fills the first groove (DY) between the first region (CEL) and the second region (WLHU), and is connected to the third region (CNCT); The first contact plug (CP12) is arranged in the first insulating layer (730) and is electrically connected to the row decoder; and the first wiring layer (IC1) is connected to the selection gate line (SGD) and the first contact Plug (CP12). |